FIELD OF THE INVENTION
The invention relates to a data memory that has at least one memory location field with memory locations. It being possible to select the memory locations by applying at least one selection signal to selection lines provided in a region of the memory locations, the selection lines possibly including word lines and/or bit lines. The date memory further has a redundancy circuit that has at least one redundancy memory location. It being possible to select the redundancy memory locations by applying at least one redundancy selection signal to redundancy selection lines provided in a region of the redundancy memory locations, the redundancy selection lines possibly containing redundancy word lines and/or redundancy bit lines. A redundancy selection line selector module which has at least one assignment memory in which an item of assignment information can be stored is provided. The redundancy selection line selector module being configured such that it is possible on the basis of the assignment information for at least one redundancy selection line to be assigned to at least one selection line. The assignment memory further has an assignment memory location with a buffer for the purpose of holding the assignment information. The assignment memory is configured such that in one operating mode of the data memory the assignment information can be transferred from the assignment memory location into the buffer.
Data memories and, in particular, semiconductor data memories are frequently produced in the following way. Firstly, a multiplicity of data memories are produced on a substrate section, which is called a wafer. After the production of the wafer, the individual data memories are tested, specifically in particular as to whether the memory locations of the memory location field and the redundancy memory locations of the redundancy circuit operate properly. In this case, a respectively different value is repeatedly written into each memory location or into each redundancy memory location, it being checked by a subsequent read operation whether the checked memory location or redundancy memory location could be properly written. If a defective memory location is determined, the redundancy selection line selector module is programmed such that an unusable memory location is assigned a redundancy memory location operating properly. This is performed such that the assigned redundancy memory location takes over the function of the memory location detected as defective. On the basis of the particular configuration of the redundancy selection line selector module, an assigned redundancy memory location can be addressed such that the memory location field gives the impression from the outside of having only properly operating memory locations.
In a subsequent step, the wafer is sawed into individual data memories. Thereafter, the individual data memories are mounted in housings and subjected again to a test, the data memories of the generic type being handed over only thereafter.
The data memories of the generic type known from U.S. Pat. No. 5,200,922 have redundancy selection line selector modules which have static memory locations in order to store an item of assignment information on the basis of which during operation a redundancy memory location is assigned to a defective memory location. Relatively high voltages are required to program these memory locations, with the result that an additional outlay on circuitry is required in the case of the data memories of the generic type. Furthermore, depending on the programming method used, relatively long programming times are required when assigning redundancy memory locations to memory locations. This is particularly objectionable, because when testing the data memories of the generic type it is also necessary to check the redundancy memory locations for their proper functioning, and this is performed by repeatedly reprogramming the redundancy memory locations. The programming times add together in the case of a multiplicity of redundancy memory locations, with the result that the checking is particularly time consuming. The checking is also attended by a high power consumption. Furthermore, there are provided in the region of the assignment memories latches into which information is written from the assignment memories during operation of the data memory of the generic type. Overall, the data memories of the generic type are expensive to produce.